The use of a thin layer of strained silicon in the channel layer of CMOS devices has been found to improve the performance characteristics of these devices. The presence of strain in the channel layer causes the individual silicon atoms within that layer to be forced farther apart or closer together in their lattice structure than would be the case in the unstrained material. The larger or smaller lattice spacing results in a change in the electronic band structure of the device such that current carriers (i.e., electrons and holes) have higher mobilities within the channel layer, thereby resulting in higher currents in the transistor and faster circuit speeds.
In CMOS devices, strained channel layers may be achieved by imparting local mechanical stresses to the device. Electron mobility, and therefore NMOS performance, may be improved by imparting tensile stress along (i.e., parallel to) the direction of current flow or orthogonal to the direction of current flow. Hole mobility, and therefore PMOS performance, may be enhanced by imparting compressive stress parallel to the direction of current flow, and by imparting tensile stress perpendicular to the direction of current flow.